VHDL simulator?


Is it possible to add an open source VHDL simulation in the platform, GHDL maybe?


Hello Ernesto,

I have no particular problem with adding “ghdl” to the platform. However, it will be an isolated tool with no other connection to the platform, since I do not have a VHDL-to-verilog converter or a VHDL parser front-end to yosys. So you could write VHDL and simulate it, but that’s about all.


Hi Tim,

Doing a quick search seems like there is a VHDL front-end plugin in the yosys repo: https://github.com/YosysHQ/yosys-plugins/tree/master/vhdl

Apparently based on this vhdl to verilog translator:

Adding these would potentially add VHDL support for the current digital flow (after some integration testing of course and hopefully worth the effort)


I can ask the Symbiotic EDA guys about the vhd2vl plugin. I see that the last contribution on github was 8 months ago, and I’m sure I’ve asked Clifford about VHDL support since then and he didn’t mention it. So I don’t know if it’s complete enough to be viable or not.

There is also freehdl, although that has the same problem as ghdl in that it would only act as a standalone simulator.

We looked at ghdl and found that it is written in ada, so it requires a lot of additional infrastructure support to get it compiled and running.