Qrouter development

Next up in qrouter development: Parsing the “VIARULE” statements from the technology LEF file. That lets qrouter generate vias at all orientations (rotations), rather than depending on specific via geometries defined in the technology LEF. This will greatly cut down on the annoying DRC errors that qrouter generates in layouts.

After that, I’ll be working on getting qrouter to do chip top-level routing so I don’t have to tell everybody that they have to do it by hand. Working toward the goal of one-button-push chip assembly!

If you have any ideas or needs for qrouter, we can discuss them here. My longer-term to-do list is quite long. . .


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On our development platform: qrouter in the newest version from git on opencircuitdesign.com. I just pulled project frequency_divider from the catalog and ran it through the qflow synthesis back-end (targeting 0.18um), and it completed with zero DRC or LVS errors. I am now testing larger designs and hope to roll this out onto the production platforms soon.

The latest version of qrouter was used on the development platform to route the RISC-V core of the Raven chip. Since all that went well in the last iteration, pushing it to production will be the next obvious step.