We are considering use of a modified RAVEN processor for an upcoming design in XH018 and have some flow/library questions. We’re covered via NDA with XFAB so we have full access to their digital libraries, verilog, etc.
We have used the opencircuitdesign flow for trials using the OSU018 and everything worked fine. Then we tried using qrouter for a “difficult” for another 180 nm process. That process is notoriously difficult to route with major direction sensitivities, and some commercial routers can’t handle the arcane DRC rules. Qrouter didn’t work either, no surprise.
XFAB routing should be a lot easier.
- The raven.v code references libraries “D_CELLS_3V” and “D_CELLS”. No issues with “D_CELLS_3V”, but “D_CELLS” does not seem to be available for the XH018 process.
1a. Do you know if “D_CELLS” is available for XH018?
1b. Alternately (even better), does qrouter now support “D_CELLS_HD” with a manageable number of DRC errors for a processor complexity type design?
- How would we handle synthesis in the eFabless synthesis considering the XFAB proprietary concerns. I looked in the knowledge base and did not seem to find insight for this.