XH018 PDK update


We have made important updates to the X-Fab 0.18um (XH018) process PDK on the efabless Open Galaxy platform.

The XH018 process on the efabless Open Galaxy platform comprises four process variants, which we have named EFXH018A, EFXH018B, EFXH018C, and EFXH018D. The “A” variant is a four-metal backend stack, the “B” variant is a five-metal backend stack, and the “C” and “D” variants are six-metal backend stacks. The topmost metal layer in “C” is a slightly thicker metal than the rest, while in “D” the penultimate metal layer is slightly thicker while the topmost metal layer is a thick metal appropriate for power redistribution. All four process variants have the same frontend options.

In order to provide our users with free and unlicensed EDA tools on the platform, it is necessary for us to develop our own PDKs, which takes considerable time and effort, as the free tools are not directly supported by the foundries. We do our best to make sure that the PDKs are correct, and we use standard format files from the foundry when we are able to do so. However, we cannot guarantee that there are not errors in the PDKs. The simulation models are based on foundry model files except for a few minor diode models for which the model used by X-Fab was not available in ngspice, and we have made substitutions where appropriate. The greatest chance for errors is in the device layouts. For these, we use a “torture test” layout of many randomly-configured components, which is cross-checked against X-Fab’s own DRC deck. The current XH018 update includes device layouts that have been extensively checked with the “torture test” method.

In order for a catalog IP block to be listed as “silicon proven” it must be fabricated as a prototype on a foundry shuttle run. For that to happen, the design must pass all foundry DRC checks. For any efabless user prototyping a design, the efabless staff must ensure that the design meets the foundry DRC requirements. In cases where the efabless tools fail to flag errors, we will work with the user to make design corrections to meet foundry DRC. For this reason, user designs intending to meet a specific X-Fab shuttle run tapeout date should be completed by the user at least one week before the X-Fab shuttle run tapeout deadline, or we cannot guarantee that the design will make it on that shuttle run.

Important note: The X-Fab MPW (Multi-Project Wafer) shuttle run is compatible with only two of the four process variants supported on the efabless platform: EFXH018A (four metal stack) and EFXH018D (six metal stack with thick top metal). For projects having any significant amount of synthesized digital logic, the six metal stack is recommended, as the four metal stack has too few routing resources for anything on the scale of a microcontroller. For example, a “hydra” class chip (simple SPI slave module controlling analog IP) could be done easily with EFXH018A, while a “raven” class chip (RISC-V microprocessor) can only be done with EFXH018D. Projects using EFXH018B or EFXH018C cannot be fabricated with the standard X-Fab shuttle runs.

Also note that any IP that uses metal backend stack resources up to but not including the thicker metal layer are compatible with all processes. Therefore some of the efabless IP like the AMUX2_3V and AMUX4_3V circuits can be used with all process variants. We do not currently enumerate all process variants any particular IP block is compatible with. To make it possible to “mix and match” such IP blocks in different process nodes, the layout tool does not enforce a match between the process variant used by the IP block and the process variant used by the layout it is placed in. So be sure to check compatibility when using IP from the catalog in other projects. When in doubt, generate a helpdesk ticket and ask.

The recent PDK update includes tool updates as well. The three most significant tool updates are qrouter, qflow, and netgen. The update to netgen (LVS tool) allows full-chip designs to be written and simulated in verilog, and then the LVS comparison is made between the verilog source and the extracted layout, avoiding the need for a schematic. The updates to qrouter (digital synthesis routing tool) greatly reduce the number of DRC errors generated by the router, especially for the EFXH018D process. However, the difficulty of routing with the “high density” standard cell sets, which includes the 3V standard cells, means that qrouter still generates an abundance of DRC errors using those standard cell sets. Since one does not generally make large digital blocks like microcontrollers in 3V logic, usually 3V logic blocks are small drivers for analog circuits and the number of DRC errors to be manually corrected is relatively small. The updates to qflow (digital synthesis flow) include automatic detection and correction of antenna violations within a digital block, and automatic progress through the entire flow when run from the GUI (with checkbox options to stop the flow at any point in the process).

For any questions regarding the PDK and tool updates, forum posts are the preferred method for any question that may be considered general interest to all platform users. If you have a question for a specific design or that relates to an issue limited to your platform session, a helpdesk ticket is appropriate.

And, as always, thank you for using the efabless platform and supporting the open source EDA effort!