Is there any guidelines or small tutorial on how to inspect and correct DRCs with Qflow?
We’ve already installed and run the whole Qflow on our server with the provided tutorial at OpenCircuit and some simple Verilog modules, using the OSU TSMC018 cells.
We now would like to start porting our RISC-V micro design to efabless. But when running the same map9v3 tutorial on the EFXH018D_HD process, we are getting 267 DRC messages that we think are related to something the tool reports as timestamp mismatches from the std cells.
Maybe I’m just being a bit lazy, but would really appreciate if someone can point me to some manual, readme or guide on how to handle DRCs and fixing them (manually via Magic or via Qflow)?
We’re using this process as we’ve done some designs with XFAB in he past, and already have a version of our RISC-V ported through the Synopsys flow, sent to fab last April, which we’d like now to replicate with open tools.